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Pipelined and Parallel Processing for Low-Power
HOMEWORK 4 EL-5105 VLSI FOR DIGITAL SIGNAL PROCESSING PIPELINED AND PARALLEL PROCESSING FOR LOW-POWER NAME: VINCENTIUS TIMOTHY STUDENT ID: 23215114 ELECTRICAL ENGINEERING STUDY PROGRAM SCHOOL OF ELECTRICAL ENGINEERING AND INFORMATICS BANDUNG INSTITUTE OF TECHNOLOGY SEMESTER I 2015/2016 I. Problem 3.11 Consider a datapath with a total capacitance of 𝐶𝑡𝑜𝑡𝑎𝑙. This datapath is pipelined by 𝑀 levels. Let 𝐶𝑙𝑎𝑡𝑐ℎ represent the total capacitance of the latches used for 1 pipelining stage. The pipelined system is operated with lower supply voltage to reduce the power consumption. Assume both systems are operated at same speed and assume the propagation delay of the latch to be negligible. Let 𝐶𝑡𝑜𝑡𝑎𝑙 = 10𝐶𝑙𝑎𝑡𝑐ℎ, 𝑉𝐷𝐷 = 4 V, and 𝑉𝑡 = 0.6 V. Calculate the power consumption of the pipelined system as a percentage if that of the sequential system for different values of 𝑀. What is the optimal 𝑀 for least power consumption? Answer The equation for pipelined systems operated at the same speed is as follows. 𝑀(𝛽𝑉0 − 𝑉𝑡)2 = 𝛽(𝑉0 − 𝑉𝑡)2 𝑀𝛽2𝑉0 2 − 2𝑀𝛽𝑉0𝑉𝑡 + 𝑀𝑉𝑡2 = 𝛽(𝑉0 − 𝑉𝑡)2 𝑉0 2𝑀𝛽2 − (2𝑉0𝑉𝑡𝑀 + (𝑉0 − 𝑉𝑡)2)𝛽 + 𝑉𝑡2𝑀 = 0 𝛽1,2 = 2𝑉0𝑉𝑡𝑀 + (𝑉0 − 𝑉𝑡)2 ± √(2𝑉0𝑉𝑡𝑀 + (𝑉0 − 𝑉𝑡)2)2 − 4𝑉0 2𝑉𝑡2𝑀2 2𝑉0 2𝑀 The following condition must be fulfilled so that the pipelined system works. 𝑉0 ′ = 𝛽𝑉0 ≥ 𝑉𝑡 ⇔ 𝛽 ≥ 𝑉𝑡 𝑉0 Input 𝑉0 = 𝑉𝐷𝐷 = 4 V and 𝑉𝑡 = 0.6 V so that 𝛽1,2 becomes as follows. 𝛽1,2 = 11.56 + 4.8𝑀 ± √−23.04𝑀2 + (11.56 + 4.8𝑀)2 32𝑀 ,𝛽 ≥ 0.15 We wish to find the 𝑀 which causes the least value of 𝛽 ≥ 0.15. In order to understand this characteristics, plot 𝛽1,2 as a function of 𝑀 as follows. Blue line: 𝛽1 Green line: 𝛽 = 0.15 Orange line: 𝛽2 20 40 60 80 100 M 0.05 0.10 0.15 0.20 0.25 0.30 0.35 Plot of as afunction of M From the plot above, we can obtain some insights as follows. If the plot of 𝛽1,2 is extended for more values of 𝑀, it will create horizontal asymptote in 𝛽 = 0.15. The valid value of 𝛽 is 𝛽1. In the other words, 𝛽2 is never valid for any 𝑀. The power consumption efficiency of the pipelined system depends on 𝑀. For 𝑀 = 10: Reduced voltage ratio: 𝛽|𝑀=10 = 0.296318 Pipelined power efficiency: 𝛽2|𝑀=10 = 0.0878044 = 8.78044% The optimal 𝑀 for least power consumption is 𝑀 → ∞. II. Problem 3.12 Calculate the power reduction of a computation if it is pipelined by 4 stages and processed using a block structure with block size 4, but is operated with the same sample rate as the original system. Assume that the original system was operated at a supply voltage of 5 V, and assume the threshold voltage 𝑉𝑡 of the CMOS process to be 0.4 V. Calculate the power consumption of the parallel-pipelined system as compared with the original system. What is the operating supply voltage of the parallel- pipelined system? Answer The equation for parallel-pipelined systems operated at the same speed is as follows. 𝑀𝐿(𝛽𝑉0 − 𝑉𝑡)2 = 𝛽(𝑉0 − 𝑉𝑡)2,𝛽 ≥ 𝑉𝑡 𝑉0 𝑀𝐿𝛽2𝑉0 2 − 2𝑀𝐿𝛽𝑉0𝑉𝑡 + 𝑀𝐿𝑉𝑡2 = 𝛽(𝑉0 − 𝑉𝑡)2 𝑉0 2𝑀𝐿𝛽2 − (2𝑉0𝑉𝑡𝑀𝐿 + (𝑉0 − 𝑉𝑡)2)𝛽 + 𝑉𝑡2𝑀𝐿 = 0 𝛽1,2 = 2𝑉0𝑉𝑡𝑀𝐿 + (𝑉0 − 𝑉𝑡)2 ± √(2𝑉0𝑉𝑡𝑀𝐿 + (𝑉0 − 𝑉𝑡)2)2 − 4𝑉0 2𝑉𝑡2𝑀2𝐿2 2𝑉0 2𝑀𝐿 ,𝛽 ≥ 𝑉𝑡 𝑉0 Input 𝑉0 = 5 V, 𝑉𝑡 = 0.4 V, 𝑀 = 4, and 𝐿 = 4, so that 𝛽1,2 becomes as follows. 𝛽1 = 0.176675,𝛽2 = 0.0362246,𝛽 ≥ 0.08 Choose 𝛽 = 𝛽1 = 0.176675. Therefore: Power supply voltage of parallel-pipelined system: 𝑉0 ′ = 𝛽𝑉0 = 0.883377 V Parallel-pipelined power efficiency: 𝛽2 = 0.0312142 = 3.12142%